As a Senior ASIC/FPGA verification Engineer at Adaptrum, we expect you to have more than 5 years of hands on testbench creation for SOC and MAC/Baseband modules, familiarity with random constraints and system Verilog constructs like arrays, queues, classes. Scope of the role includes the following:
- Create a testbench specification and test plan.
- Implement testbench based on the specification.
- Understand RTL design and create directed and random test (in Verilog or in C) to achieve high coverage.
- Validate RTL in simulation, gate simulation, and ASIC/FPGA bring-up.
- Over 5 years of experience in ASIC/FPGA verification.
- Strong System Verilog programming skills including toplevel and unit-level verification.
- Experience validating and debugging high-speed interfaces (USB, DDR) and networking protocols (Ethernet) on ASIC/FPGA.
- Experience validating and debugging multi processor AXI interconnected ASIC/FGPA system.
- Knowledge of MAC or baseband verification flow is a plus.
- Experience working with software engineer to validate software and hardware integration.
- Expert knowledge of PERL, Makefile, System Verilog to automate test generation and checking.