As a FPGA Design Engineer at Adaptrum, we expect you to have more than
5 years of hands on FPGA validation experience, familiarity with IO constraints, and an understanding
of SOC and processor+bus architecture. Scope of the role includes the following:
- Create a micro-architecture specification and test plan
- Implement RTL based on the specification
- Synthesize RTL and close timing with proper IO constraints
- Validate RTL in simulation, gate simulation, and FPGA bring-up
- Over 5 years of experience in ASIC/FPGA design and verification.
- Strong Verilog/VHDL programming skills including unit-level verification.
- Experience validating and debugging high-speed interfaces (USB, DDR) and networking protocols
(Ethernet) on FPGA.
- Experience validating and debugging multi processor FGPA system.
- Experience working with software engineer to validate software and hardware integration.
- Expert knowledge of synthesis constraints (IO and intra chip) and ability to setup synthesis
constraints from scratch.
- Experience with Xilinx FPGAs, ILA and Vivado.