As an ASIC SOC Design Engineer at Adaptrum, we expect you to have more than 5 years of hands on SOC design and validation experience, familiarity with IO constraints, and an understanding of SOC and processor+bus architecture. Scope of the role includes the following:
- Create a micro-architecture specification and test plan.
- Implement RTL based on the specification.
- Synthesize RTL and close timing with proper IO constraints.
- Validate RTL in simulation, gate simulation/power simulation, UPF flow, and chip bring-up.
- Over 5 years of experience in ASIC design and verification.
- Strong Verilog/VHDL programming skills including unit-level verification.
- Experience integrating and validating high-speed interfaces (USB, DDR) and networking protocols (Ethernet) on ASIC.
- Experience designing and validating peripherals SPI, QSPI, UART, I2C, SDIO, DMA, AXI bus arbiter/monitor on ASIC.
- Experience validating and debugging multi processor ASIC system.
- Experience working with software engineer to validate software and hardware integration.
- Expert knowledge of synthesis constraints (IO and intra chip) and ability to setup synthesis constraints from scratch.
- Experience with Design Compiler, Formal Verification, PrimeTime, CDC, Lint